Resource Efficient LDPC Decoders: From Algorithms to Hardware Architectures

This book takes a practical hands-on approach to developing low complexity algorithms and transforming them into working hardware. It follows a complete design approach - from algorithms to hardware architectures - and addresses some of the challenges associated with their design, providing insight into implementing innovative architectures based on low complexity algorithms. The reader will learn: Modern techniques to design, model and analyze low complexity LDPC algorithms as well as their hardware implementationHow to reduce computational complexity and power consumption using computer aided design techniquesAll aspects of the design spectrum from algorithms to hardware implementation and performance trade-offs Provides extensive treatment of LDPC decoding algorithms and hardware implementationsProvides a systematic guidance, giving a basic understanding of LDPC codes and decoding algorithms and providing practical skills in implementing efficient LDPC decoders in hardware INDICE: 1. Introduction 2. Overview of LDPC codes 3. Highly flexible LDPC matrices 4. Efficient LDPC encoding algorithms 5. Reduced complexity LDPC decoding algorithms 6. Hardware architectures for LDPC codes 7. Prototyping LDPC codes in the hardware 8. Applications of resource efficient LDPC decoders

• ISBN: 978-0-12-811255-7
• Editorial: Academic Press
• Encuadernacion: Rústica
• Páginas: 475
• Fecha Publicación: 01/10/2017
• Nº Volúmenes: 1
• Idioma: Inglés