Low-Power High-Speed ADCs for Nanometer CMOS Integrationandnbsp;is about the design and implementation of ADC in nanometer CMOS processes that achieve lower power consumption for a given speed and resolution than previous designs, through architectural and circuit innovations that take advantage of unique features of nanometer CMOS processes. A phase lock loop (PLL) clock multiplier hasalso been designed using new circuit techniques and successfully tested. 1) A1.2V, 52mW, 210MS/s 10-bit two-step ADC in 130nm CMOS occupying 0.38mm2. Using offset canceling comparators and capacitor networks implemented with small value interconnect capacitors to replace resistor ladder/multiplexer in conventional sub-ranging ADCs, it achieves 74dB SFDR for 10MHz and 71dB SFDR for 100MHz input. 2) A 32mW, 1.25GS/s 6-bit ADC with 2.5GHz internal clock in 130nm CMOS. A new type of architecture that combines flash and SAR enables the lowest power consumption, 6-bit andgt;1GS/s ADC reported to date. Implementation detail of three state-of-the-art low-power high-performance ADC and clock multiplier PLL designs using unique architectures Concise and graphical explanation ofkey points in ADC/PLL design at both architecture and circuit level Theory backed by extensive measurement results from actual silicon INDICE: List of Figures. List of Tables. Preface. 1. Introduction. 2. A 52mW 10b 210MS/s Two-Step ADC for Digital IF Receivers in 130nm CMOS. 3. A 32mW 1.25GS/s 6b 2b/Step SAR ADC in 130nm Digital CMOS 47. 4. A 0.4ps-RMS-Jitter 1-3GHz Clock Multiplier PLL Using Phase-Noise Preamplification. 5. Conclusions and Future Directions. References.
- ISBN: 978-1-4020-8449-2
- Editorial: Springer
- Encuadernacion: Cartoné
- Páginas: 150
- Fecha Publicación: 01/05/2008
- Nº Volúmenes: 1
- Idioma: Inglés