This book uses a ‘learning by doing’ approach to introduce the HDL (hardware description languages) and FPGA development process to designers through a series of hands-on experiments. A wide range of examples is included, from a simple gate-level circuit to an embedded system with an eight-bit soft-core microcontroller and customized I/O peripherals. All examples can be synthesized and physically tested on an actual FPGA prototyping board. INDICE: Preface. Acknowledgments. PART I: BASIC DIGITAL CIRCUITS. 1. Gate-level combinational circuit. 1.1 Introduction. 1.2 General description. 1.2.1 Basic lexical rules. 1.2.2 Library and package. 1.2.3 Entity declaration. 1.2.4 Data type and operators. 1.2.5 Architecture body. 1.2.6 Code of a 2-bit comparator. 1.3 Structural description. 1.4 Testbench. 1.5 Bibliographic notes. 1.6 Suggested experiments. 1.6.1 Code for gate-level greater-than circuit. 1.6.2Code for gate-level binary decoder. 2. Overview of FPGA and EDA software. 2.1Introduction. 2.2 FPGA. 2.2.1 Overview of general FPGA device. 2.2.2 Overviewof Xilinx Spartan-3 device. 2.3 Overview of Digilent S3 board. 2.4 Design flow. 2.5 Overview of Xilinx ISE project navigator. 2.6 Short tutorial of ISE project navigator. 2.6.1 Create the design project and HDL codes. 2.6.2 Create a testbench and perform RTL simulation. 2.6.3 Add a constraint file and synthesize and implement the code. 2.6.4 Generate and download the configuration file to FPGA devices. 2.7 Short tutorial of ModelSim HDL simulator. 2.8 Bibliographic notes. 2.9 Suggested experiments. 2.9.1 Gate-level greater-than circuit. 2.9.2 Gate-level binary decoder. 3. RT-level combinational circuit. 3.1 Introduction. 3.2 RT-level components. 3.2.1 Relational operators. 3.2.2 Arithmetic operators. 3.2.3 Other synthesis related VHDL constructs. 3.2.4 Summary. 3.3 Routing circuit with concurrent assignment statements. 3.3.1 Conditional signal assignment statement. 3.3.2 Selected signal assignment statement. 3.4 Modeling with process. 3.4.1 Process. 3.4.2 Sequential signal assignment statement. 3.5Routing circuit with if and case statements. 3.5.1 If statement. 3.5.2 Case statement. 3.5.3 Comparison to concurrent statements. 3.5.4 Unintended memory. 3.6 Constant and generic. 3.6.1 Constant. 3.6.2 Generic. 3.7 Design examples. 3.7.1 Hexadecimal digit to seven-segment LED decoder. 3.7.2 Sign-magnitude adder. 3.7.3 Barrel shifter. 3.7.4 A simplified floating-point adder. 3.8 Bibliographic notes. 3.9 Suggested experiments. 3.9.1 Multi-function barrel shifter. 3.9.2 Dual priority encoder. 3.9.3 BCD incrementor. 3.9.4 Floating-point greater-than circuit. 3.9.5 Floating-point and signed integer conversion circuit. 3.9.6 Enhanced floating-point adder. 4. Regular Sequential Circuit../…16. PicoBlaze I/O Interface. 16.1 Overview. 16.2 Output port. 16.2.1 Output instructionand timing. 16.2.2 Output interface. 16.3 Input port. 16.3.1 Input instruction and timing. 16.3.2 Input interface. 16.4 Square program with switch and seven-segment LED display interface. 16.4.1 Output interface. 16.4.2 Input interface. 16.4.3 Assembly code development. 16.4.4 VHDL code development. 16.5 Square program with combinational multiplier and UART console. 16.5.1 Multiplier interface. 16.5.2 UART interface. 16.5.3 Assembly code development. 16.5.4 VHDL code development. 16.6 Bibliographic notes. 16.7 Suggested experiments. 16.7.1Low-frequency counter I. 16.7.2 Low frequency counter II. 16.7.3 Auto-scaled low-frequency counter. 16.7.4 Basic reaction timer with software timer. 16.7.5Basic reaction timer with hardware timer. 16.7.6 Enhanced reaction timer. 16.7.7 Small-screen mouse scribble circuit. 16.7.8 Full-screen mouse scribble circuit. 16.7.9 Enhanced rotating banner. 16.7.10 Pong game. 16.7.11 Text editor.17. PicoBlaze Interrupt Interface. 17.1 Overview. 17.2 Interrupt handling in PicoBlaze. 17.2.1 Software processing. 17.2.2 Timing. 17.3 External interface.17.3.1 Single interrupt request. 17.3.2 Multiple interrupt requests. 17.4 Software development considerations. 17.4.1 Interrupt as alternative scheduling scheme. 17.4.2 Development of interrupt service routine. 17.5 Design example. 17.5.1 interrupt interface. 17.5.2 Interrupt service routine development. 17.5.3 Assembly code development. 17.5.4 VHDL code development. 17.6 Bibliographic notes. 17.7 Suggested experiments. 17.7.1 Alternative timer interrupt service routine. 17.7.2 Programmable timer. 17.7.3 Set-button interrupt service routine. 17.7.4 Interrupt interface with two requests. 17.7.5 Four-request interruptcontroller. Appendix A: Sample VHDL templates. A.1 General VHDL constructs. A.1.1 Overall code structure. A.1.2 Component instantiation. A.2 Combinational circuits. A.2.1 Arithmetic operations. A.2.2 Fixed-amount shift operations. A.2.3 Routing with concurrent statements. A.2.4 Routing with case and if statements. A.2.5 Combinational circuit using process. A.3 Memory Components. A.3.1 Register template. A.3.2 Register file. A.4 Regular sequential circuits. A.5 FSM. A.6 FSMD. A.7 S3 board constraint file (s3.ucf). References.
- ISBN: 978-0-470-18531-5
- Editorial: John Wiley & Sons
- Encuadernacion: Tela
- Páginas: 440
- Fecha Publicación: 15/02/2008
- Nº Volúmenes: 1
- Idioma: Inglés