Since register transfer level (RTL) design is less about being a bright engineer, and more about knowing the downstream implications of your work, this book explains the impact of design decisions taken that may give rise later in the product lifecycle to issues related to testability, data synchronization across clock domains, synthesizability, power consumption, routability, etc., allwhich are a function of the way the RTL was originally written. Readers will benefit from a highly practical approach to the fundamentals of these topics, and will be given clear guidance regarding necessary safeguards to observe during RTL design. Provides a highly accessible, single-source reference to all key topics essential to an RTL designer;. Describes in detail specific actions/cautions that designer needs to consider in design to avoid problems in downstream implementation;. Covers content based on practical experience with numerous real designs from large semiconductor design companies. INDICE: Introduction to RTL Designs; Ensuring RTL Intent; Static Timing Analysis (STA); Clock Domain Crossing (CDC); Power; Design for Test; Timing Exceptions; Congestion; Conclusions.
- ISBN: 978-1-4419-9295-6
- Editorial: Springer New York
- Encuadernacion: Cartoné
- Páginas: 192
- Fecha Publicación: 17/05/2011
- Nº Volúmenes: 1
- Idioma: Inglés