High-level synthesis: from algorithm to digital circuit

High-level synthesis: from algorithm to digital circuit

Coussy, P.
Morawiec, A.

83,15 €(IVA inc.)

The successful usage of Hardware Description Languages like VHDL and Verilog in design flows is mainly due to the availability of efficient synthesis methods and tools that enable the translation of RTL designs into optimized gate-level implementations. Many expect that the same approach could be effectively adapted at higher levels of abstraction. In the SoCs context, the traditional IC design methodology relying on EDA tools used in a two stages design flow - aVHDL/Verilog RTL specification, followed by logical and physical synthesis - is indeed no more suitable. Thus, actual complex SoCs need new ESL level toolsin order to raise the specification abstraction level up to the algorithmic /behavioral one. However, in order to provide the designers with an efficient automated path to implementation, new high-level synthesis tools and approaches are required. Extensive presentation of the leading research activities in HLS Presentation of strengths of the available HLS technologies User needs and application domains analysis Overview of available EDA tool solutions and their applicability to design problems INDICE: Preface. 1: User Needs. 2: HLS: A Retrospective. 3: Catapult(R) Synthesis. 4: Algorithmic Synthesis using PICO. 5: High-Level SystemC Synthesis with Forte's Cynthesizer. 6: AutoPilotTM: A Platform-Based ESL Synthesis System. 7: ‘All-in-C’ SoC Synthesis and Verification with CyberWorkBench. 8: Bluespec: A General-Purpose Approach to High Level Synthesis based on Atomic Transactions. 9: GAUT: A High-Level Synthesis Tool for DSP Applications. 10: User Guided High Level Synthesis. 11: Synthesis of DSP Algorithms from Infinite Precision Specifications. 12: High-Level Synthesis of loops using the Polyhedral Model. 13: Operation Scheduling: Algorithms and Applications. 14: Exploiting Bit-Level Design Techniques in Behavioural Synthesis. 15: High-Level Synthesis Algorithms for Power and Temperature Minimization.

  • ISBN: 978-1-4020-8587-1
  • Editorial: Springer
  • Encuadernacion: Cartoné
  • Páginas: 300
  • Fecha Publicación: 01/06/2008
  • Nº Volúmenes: 1
  • Idioma: Inglés