Offset reduction techniques in high-speed analog-to-digital converters: analysis, design and tradeoffs

Offset Reduction Techniques in High-Speed Analog-to-Digital Converters analyzes, describes the design, and presents test results of Analog-to-Digital Converters (ADCs) employing the three main high-speed architectures: flash, two-step flash and folding and interpolation. The advantages and limitations of each one are reviewed, and the techniques employed to improve their performance are discussed. All high-speed ADC architectures (flash, two-step, folding and interpolation) covered in detail The performance parameters and trade-offs encountered in each of the ADC’s sub-blocks are analysed Most exhaustive study ever performed about averaging is presented Offset sampling techniques that yield a nearly offset free, high-speed, comparator are described INDICE: Preface. List of Symbols and Abbreviations. 1 High-Speed ADC Architectures. 2 Averaging Technique - DC Analysis and Termination. 3 Averaging Technique - Transient Analysis and Automated Design. 4 Integrated Prototypes Using Averaging. 5 Offset Cancellation Methods. 6 Conclusions. Appendix A: Averaging With Piecewise Linear Differential Pairs. Appendix B: Mismatches In The Resistors Of The Aveaging Network. Appendix C Averaging In Folding Stages. References. Index.

• ISBN: 978-1-4020-9715-7
• Editorial: Springer
• Encuadernacion: Cartoné
• Páginas: 350
• Fecha Publicación: 01/04/2009
• Nº Volúmenes: 1
• Idioma: Inglés