Computer architecture: a quantitative approach

For over 20 years, Computer Architecture: A Quantitative Approach has been considered essential reading by instructors, students, and practitioners of computer design. The latest edition of this classic textbook is fully revised with the latest developments in processor and system architecture. It now features examples from the RISC-V  (RISC Five) instruction set architecture, a modern RISC instruction set developed and designed to be a free and openly adoptable standard.  It also includes a new chapter on domain-specific architectures and an updated chapter on warehouse-scale computing that features the first public information on Google's newest WSC. True to its original mission of demystifying computer architecture, the sixth edition of  Computer Architecture: A Quantitative Approach continues its longstanding tradition of focusing on the areas where the most exciting computing innovation is happening, while always keeping an emphasis on good engineering design. Includes a new chapter on domain-specific architectures, explaining how they are only path forward for improved performance and energy efficiency given the end of Moore's Law and Dinnard scaling. Features first publication of several DSAs from industry.Features extensive updates to the chapter on warehouse-scale computing, with first public information on the newest Google WSC.Updates to other chapters include new material dealing with the use of stacked DRAM; data on the performance of new Nvidia Pascal GPU vs new AVX/512 Intel Skylake CPU; and extensive additions to content covering multicore architecture and organization. Trademark Putting It All Together sections appear near the end of every chapter, providing real-world technology examples that demonstrated the principles covered in each chapter.Includes review appendices in the printed text and additional reference appendices available onlineIncludes updated and improved case studies and exercises. INDICE: Printed Text 1. Fundamentals of Quantitative Design and Analysis 2. Memory Hierarchy Design 3. Instruction-Level Parallelism and Its Exploitation 4. Data-Level Parallelism in Vector, SIMD, and GPU Architectures 5. Multiprocessors and Thread-Level Parallelism 6. The Warehouse-Scale Computer 7. Domain Specific Architectures Appendix A. Instruction Set Principles B. Review of Memory Hierarchy C. Pipelining: Basic and Intermediate Concepts Online D. Storage Systems E. Embedded Systems F. Interconnection Networks G. Vector Processors H. Hardware and Software for VLIW and EPIC I. Large-Scale Multiprocessors and Scientific Applications J. Computer Arithmetic  K. Survey of Instruction Set Architectures L. Historical Perspectives

• ISBN: 978-0-12-811905-1
• Editorial: Morgan Kaufmann
• Encuadernacion: Rústica
• Páginas: 856
• Fecha Publicación: 01/12/2017
• Nº Volúmenes: 1
• Idioma: Inglés