Metamodeling driven IP reuse for system-on-a-chip integration and verification

This cutting-edge resource offers electrical/computer engineers an in-depth understanding of metamodeling approaches for the reuse of intellectual properties (IPs) in the form of design or verification components. The book covers theessential issues associated with fast and effective integration of reusable design components into a system-on-a-chip (SoC) to achieve faster design turn-around time. Moreover, it addresses key factors related to the use of reusable verification IPs for a "write once, use many times" verification strategy - another effective approach that can attain a faster product design cycle. Electrical engineers, developers of system-on-a-chip components, and computer-aided chip designers. INDICE: Introduction. Background. Related Work. A Metamodel for Component Composition. IP Reflection & Selection. Typing Problems in IP Composition. IP Composition. Checker Generation for IP Verification. A Metamodel for Microprocessors. Design Fault Directed Test Generation. Model-Driven System Level Validation. Conclusion & Future Work. Bibliography. Vita.

• ISBN: 978-1-59693-424-5
• Editorial: Artech House
• Encuadernacion: Desconocida
• Páginas: 330
• Fecha Publicación: 01/06/2009
• Nº Volúmenes: 1
• Idioma: Inglés