Design of System on a Chip is the first of two volumes addressing the design challenges associated with new generations of the semiconductor technology. The various chapters are the compilations of tutorials presented at workshops inBrazil in the recent years by prominent authors from all over the world. In particular the first book deals with components and circuits. Device models have to satisfy the conditions to be computationally economical in addition to beaccurate and to scale over various generations of technology. In addition thebook addresses issues of the parasitic behavior of deep sub-micron components, such as parameter variations and sub-threshold effects. Furthermore various authors deal with items like mixed signal components and memories. We wind up with an exposition of the technology problems to be solved if our community wants to maintain the pace of the "International Technology Roadmap for Semiconductors" (ITRS). INDICE: Designs of System on a Chip. Introduction; R. Reis, J.A.G. Jess. BJT Modeling with VBIC; C.C. McAndrew. A MOS Transistor Model for Mixed Analog-digital Circuit Design and Simulation; M. Bucher, C. Lallement, F. Krummenacher, C. Enz. Efficient Statistical Modeling for Circuit Simulation; C.C. McAndrew. Retargetable Application-driven Analog-digital Block Design; J.E. Franca. Robust Low Voltage Power Analog VLSI Design; T.B. Tarim, C.H. Lin, M. Ismail. Ultralow-voltage memory circuits; K. Itoh. Low-voltage Low-power High-speed I/OBuffers; R. Leung. Microelectronics toward 2010; T. Yanagawa, S. Bampi, G. Wirth. Index of Authors.
- ISBN: 978-1-4419-5454-1
- Editorial: Springer
- Encuadernacion: Rústica
- Fecha Publicación: 14/03/2012
- Nº Volúmenes: 1
- Idioma: Inglés