Statistical performance analysis and modeling techniques for nanometer VLSI designs

Since process variation and chip performance uncertainties have become more pronounced as technologies scale down into the nanometer regime, accurate and efficient modeling or characterization of variations from the device to the architecture level have become imperative for the successful design of VLSI chips. This book provides readers with tools for variation-aware design methodologies and computer-aided design (CAD) of VLSI systems, in the presence of process variations at the nanometer scale. It presents the latest developments for modeling and analysis, with a focus on statistical interconnect modeling, statistical parasitic extractions, statistical full-chip leakage and dynamic power analysis considering spatial correlations, statistical analysis and modeling for large global interconnects and analog/mixed-signal circuits.. Provides readers with timely, systematic and comprehensive treatments of statistical modeling and analysis of VLSI systems with a focus on interconnects, on-chip power grids and clock networks, and analog/mixed-signal circuits; Helps chip designers understand the potential and limitations of their design tools, improving their design productivity; Presents analysis of each algorithm with practical applications in the context of real circuit design; Includes numerical examples for the quantitative analysis and evaluation of algorithms presented.. Provides readers with timely, systematic and comprehensive treatments of statistical modeling and analysis of VLSI systems with a focus on interconnects, on-chip power grids and clock networks, and analog/mixed-signal circuits; Helps chip designers understand the potential and limitations of their design tools, improving their design productivity; Presents analysis of each algorithm with practical applications in the context of real circuit design; Includes numerical examples for the quantitative analysis and evaluation of algorithms presented. Provides readers with timely, systematic and comprehensive treatments of statistical modeling and analysis of VLSI systems with a focus on interconnects, on-chip power grids and clock networks, and analog/mixed-signal circuits. Helps chip designers understand the potential and limitations of their design tools, improving their design productivity. Presents analysis of each algorithm with practical applications in the context of real circuit design Includes numerical examples for the quantitative analysis and evaluation of algorithms presented. INDICE: Part I: Fundamentals. Introduction. Fundamentals of Statistical Analysis. Part II: Statistical Full Chip Power Analysis. Traditional StatisticalLeakage Power Analysis Methods. Statistical Leakage Power Analysis by Spectral Stochastic Method. Linear Statistical Leakage Analysis by Virtual Grid BasedModeling. Statistical Dynamic Power Estimation Techniques. Statistical Total Power Estimation Techniques. Part III: Variational On-Chip Power Delivery Network Analysis. Statistical Power Grid Analysis Considering Log-normal Leakage Current Variations. Statistical Power Grid Analysis by Stochastic Extended Krylov Subspace Method. Statistical Power Grid Analysis by Variational Subspace Method. Part IV: Statistical Interconnect Modeling and Extractions. Statistical Capacitance Modeling and Extraction. Incremental Extraction of Variational Capitance. Statistical Inductance Modeling and Extraction. Part V: Statistical Analog and Yield Analysis and Optimization Techniques. Performance Bound Analysis of Variational Linearized Analog Circuits.- Stochastic Analog Mismatch Analysis. Statistical Yield Analysis and Optimization. Voltage Binning Technique for Yield Optimization.

• ISBN: 978-1-4614-0787-4
• Editorial: Springer New York
• Encuadernacion: Cartoné
• Páginas: 318
• Fecha Publicación: 31/03/2012
• Nº Volúmenes: 1
• Idioma: Inglés