Integrated circuit design: a circuits and systems perspective: international version

For both introductory and advanced courses in VLSI design, this authoritative, comprehensive textbook is highly accessible to beginners, yet offers unparalleled breadth and depth for more experienced readers. The Fourth Edition of CMOS VLSI Design: A Circuits and Systems perspective presents broad and in-depth coverage of the entire field of modern CMOS VLSI Design. The authors draw upon extensive industry and classroom experience to introduce today's most advanced and effective chip design practices. They present extensively updated coverage of every key element of VLSI design, and illuminate the latest design challenges with 65 nm process examples. This book contains unsurpassed circuit-level coverage, as well as a rich set of problems and worked examples that provide deep practical insight to readers at all levels. INDICE: Chapter 1 Welcome to VLSI 1.1 A Brief History ... 1 1.2 Preview...6 1.3 MOS Transistors... 6 1.4 CMOS Logic... 9 1.4.1 The Inverter 9 1.4.2 TheNAND Gate 9 1.4.3 CMOS Logic Gates 9 1.4.4 The NOR Gate 11 1.4.5 Compound Gates 11 1.4.6 Pass Transistors and Transmission Gates 12 1.4.7 Tristates 14 1.4.8 Multiplexers 15 1.4.9 Sequential Circuits 16 1.5 CMOS Fabrication and Layout... 19 1.5.1 Inverter Cross-Section 19 1.5.2 Fabrication Process 20 1.5.3 Layout Design Rules 24 1.5.4 Gate Layouts 27 1.5.5 Stick Diagrams 28 1.6 Design Partitioning ... 29 1.6.1 Design Abstractions 30 1.6.2 Structured Design 31 1.6.3 Behavioral, Structural, and Physical Domains 31 1.7 Example: A Simple MIPS Microprocessor... 33 1.7.1 MIPS Architecture 33 1.7.2 Multicycle MIPS Microarchitectures 34 1.8 Logic Design... 38 1.8.1 Top-Level Interfaces 38 1.8.2 Block Diagrams 38 1.8.3 Hierarchy 40 1.8.4 Hardware Description Languages 40 1.9 Circuit Design... 42 1.10 Physical Design... 45 1.10.1 Floorplanning 45 1.10.2 Standard Cells 48 1.10.3 Pitch Matching 50 1.10.4 Slice Plans 50 1.10.5 Arrays 51 1.10.6 Area Estimation 51 1.11 Design Verification... 53 1.12 Fabrication, Packaging, and Testing... 54 Summary and a Look Ahead 55 Exercises 57 Chapter 2Devices 2.1 Introduction... 61 2.2 Long-Channel I-V Characteristics... 64 2.3C-V Characteristics... 68 2.3.1 Simple MOS Capacitance Models 68 2.3.2 Detailed MOS Gate Capacitance Model 70 2.3.3 Detailed MOS Diffusion Capacitance Model 72 2.4 Nonideal I-V Effects... 74 2.4.1 Mobility Degradation and Velocity Saturation 75 2.4.2 Channel Length Modulation 78 2.4.3 Threshold Voltage Effects79 2.4.4 Leakage 80 2.4.5 Temperature Dependence 85 2.4.6 Geometry Dependence86 2.4.7 Summary 86 2.5 DC Transfer Characteristics... 87 2.5.1 Static CMOS Inverter DC Characteristics 88 2.5.2 Beta Ratio Effects 90 2.5.3 Noise Margin 91 2.5.4 Pass Transistor DC Characteristics 92 2.6 Pitfalls and Fallacies... 93Summary 94 Exercises 95 Chapter 3 Speed 3.1 Introduction... 99 3.1.1 Definitions 99 3.1.2 Timing Optimization 100 3.2 Transiet Response ...101 3.3 RC DelayModel ...104 3.3.1 Effective Resistance 104 3.3.2 Gate and Diffusion Capacitance 105 3.3.3 Equivalent RC Circuits 105 3.3.4 Transient Response 106 3.3.5 Elmore Delay 108 3.3.6 Layout Dependence of Capcitance 111 3.3.7 Determining Effective Resistance 112 3.4 Linear Delay Model ... 113 3.4.1 Logical Effort 114 3.4.2 Parasistic Delay 114 3.4.3 Delay in a Logic Gate 116 3.4.4 Drive 117 3.4.5 Extracting Logical Effort from Datasheets 117 3.4.6 Limitations to the Linear Delay Model 118 3.5 Logical Effort of Paths ... 121 3.5.1 Delay in Multistage Logic Networks 121 3.5.2 Choosing the Best Number of Stages 124 3.5.3 Example 126 3.5.4 Summary and Observations 127 3.5.5 Limitations of Logical Effort 129 3.5.6 Iterative Solutions for Sizing 129 3.6 Timing analysis Delay Models... 131 3.6.1 Slope-Based Linear Model 131 3.6.2 Nonlinear Delay Model 132 3.6.3 Current Source Model 132 3.7 Pitfalls and Fallacies ... 132 3.8 Historical Perspective ... 133 Summary 134 Exercises 134 Chapter 4 Power 4.1 Introduction ... 139 4.1.1 Definitions 140 4.1.2 Examples 142 4.1.3 Sourches of Power Dissipation 142 4.2 Dynamic Power... 143 4.2.1 Activity Factor 144 4.2.2. Capacitance 146 4.2.3 Voltage 148 4.2.4 Frequency 150 4.2.5 Short-Circuit Current 151 4.2.6 Resonant Circuits 151 4.3 Static Powerl ... 152 4.3.1 Static Power sources 152 4.3.2 Power Gating 155 4.3.3 Multiple Threshold Voltages and Oxide Thicknesses 157 4.3.4 Variable Threshold Voltages 157 4.3.5 Input Vector Control 158 4.4 Energy-Delay Optimization ...158 4.4.1 Minimum Energy 158 4.4.2 Minimum Energy-Delay Product 161 4.4.3 Minimum Energy Under a Delay Constraint 161 4.5Low Power Architectures... 162 4.5.1 Microarchitecture 162 4.5.2 Parallelism and Pipelining 162 4.5.3 Power Management Modes 163 4.7 Pitfalls and Fallacies... 164 4.8 Historical Perspective ... 165 Summary 167 Exercises 167 Chapter 5 Wires 5.1 Introduction ... 169 5.1.1 Wire Geometry 169 5.1.2 Example: Intel Metal Stacks 170 5.2 Interconnect Modeling ... 171 5.2.1 Resistance 172 5.2.2 Capacitance 173 5.2.3 Inductance 176 5.2.4 Skin Effect 177 5.2.5 Terperature Dependence 178 5.3 Interconnect Impact ... 178 5.3.1 Delay 178 5.3.2 Energy 1805.3.3 Crosstalk 180 5.3.4 Inductive Effects 182 5.3.5 An Aside on Effective Resistance and Elmore Delay 185 5.4 Interconnect Engineering... 187 5.4.1 Width, Spacing and Layer 187 5.4.2 Repeaters 188 5.4.3 Crosstalk Contol 190 5.4.4 Low-Swing Signaling 192 5.4.5 Regenerators 194 5.5 Logical Effort with Wires...194 5.6 Pitfalls and Fallacies ... 195 Summary 196 Exercises 196 Chapter 6 Scaling, Reliability and Variability 6.1 Introduction ... 199 6.2 Variability ...199 6.2.1 Supply Voltage 200 6.2.2 Termparature 200 6.2.3 Process Variation 201 6.2.4 Design Corners 202 6.3 Reliability ... 204 6.3.1 Reliability Terminology 204 6.3.2 Oxide Wearout 205 6.3.3 Interconnect Wearout 207 6.3.4 Soft Errors 209 6.3.5 Overvoltage Failure 210 6.3.6 Latchup 211 6.4 Scaling ... 212 6.4.1 Transistor Scaling 213 6.4.2 Interconnect Scaling 215 6.4.3 International Technology Roadmap for Semiconductors 216 6.4.4 Impacts on Design 217 6.5 Statistical Analysis of Variability ... 221 6.5.1 Properties of Random Variables 221 6.5.2 Variation Sources 224 6.5.3 Variation Impacts 227 6.6 Variation-Tolerant Design. Etc.

• ISBN: 978-0-321-69694-6
• Editorial: Pearson/Prentice Hall
• Encuadernacion: Rústica
• Páginas: 864
• Fecha Publicación: 01/05/2010
• Nº Volúmenes: 1
• Idioma: Inglés